Silicon Co-Design | Chad | Substack

Expert-driven interdisciplinary deep-dives into the AI HW Infrastructure stack from pure fundamentals. Click to read Silicon Co-Design, by Chad, a Substack publication with thousands of subscribers.

www.siliconcodesign.com

Silicon Co-Design | Chad | Substack · Sep 14, 2026

SEMICONDUCTOR DESIGN AND FABRICATION

Co-Packaged Optics for 224Gbps+ Scale-Up: An All-In-One Overview

A system breakdown of challenges for every technology component of CPO: packaging, PIC, laser, and EIC

BOSTON MAINTEL

Silicon Co-Design | Chad | Substack · Aug 18, 2026

HIGH PERFORMANCE COMPUTING

A System-Level Overview of Scale-up AI Infrastructure Racks (Part 1: Network Architecture)

How high-speed fabrics parallelize massive workloads across AI racks, the cross-domain co-design trade-offs involved, and all of the subsystems underneath

Silicon Co-Design | Chad | Substack · Aug 14, 2026

SEMICONDUCTOR DESIGN AND FABRICATION

A Deep Dive into SRAM: The Staging Ground of LLM Inference

Fundamentals of SRAM and how SRAM constraints affect array size scaling and LLM inference performance

Silicon Co-Design | Chad | Substack · Aug 04, 2026

SEMICONDUCTOR DESIGN AND FABRICATION

Design Automation Conference 2026 - The Bottlenecks that Limit AI Use in Chip Design

VLSI fundamentals, vibe coding RTL, why chip design takes so long, and key bottlenecks that limit AI use in chip design to quality-of-life enhancements

IAN CUTRESSWILLIAM WANG

Silicon Co-Design | Chad | Substack · Jul 15, 2026

HIGH PERFORMANCE COMPUTING

A Comprehensive Deep Dive into High-Speed HBM5 Interconnect: Signal Integrity and Co-Design Challenges

How transmission line effects and power-supply induced jitter make high-speed HBM interconnect scaling one of the most challenging co-design issues in AI racks